Motorola Politics ~
A USENET post :: An Engineering Parable ...
Up until Motorola stock took a beating - starting spring
1994 - over [bad???] business decisions to invest heavily in emerging, troubled world
markets, the "circle M ranch" was an absolutely great place to work. There was so much
going on it was hard - if not impossible - to butt heads with anyone. Assuming you were
a hard worker, people basically stepped aside since they knew your efforts would ensure
their RONA (Return On Net Assets) bonus money. I worked in an applied research group
creating new technologies which were ultimately packaged as mixed signal integrated
circuits.
Ahh, but then times got tough. Indeed the level of internal politics went up by over
1,000,000% as rumors of massive layoffs started circulating. In our little research
group a newly hired, second CAD manager was struggling with the politics and wanted
desperately to make his mark. Unfortunately he lacked political savvy and engineering
experience; he also had zero talent as a manager in any capacity.
With regards to EDA tools, we actually had access to all 1st, most
2nd, and many of the 3rd tier EDA tools in the research group.
With just about 30 engineers in the group, we had a average EDA budget of over $5M per
year for new tools in the mid nineties (this was just for EDA software). With this
level of tools variety, engineers had ample access to the "right hammer" for the
job.
In a dash of brilliance, or sheer stupidity, I authored the following post and launched it to
the Internet - anonymously of course. The response to the post was actually quite
interesting - although I never posted a follow-up, my only motivation was to mock the
level of politics and ignorance the working engineers experienced on a day to day
basis.
Anyway, here is an original copy of that news group post.
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Newsgroups: comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi
From: an361748@anon.penet.fi
X-Anonymously-To: comp.cad.synthesis,comp.lang.verilog,comp.lang.vhdl,comp.lsi
Organization: Anonymous forwarding service
Reply-To: an361748@anon.penet.fi
Date: Mon, 21 Aug 1995 16:50:53 UTC
Subject: An Engineering Parable
Lines: 191
Once upon a time...
...there was an engineer who wished to build an IC. He had built
chips before, writing register transfer level Verilog HDL, and
simulating, synthesizing, and performing detailed timing analysis
with tools from Cadence Design Systems. The engineer also contemplated
performing his own mask place and route since Cadence had linked
their synthesis tool to their well established P&R engine technology.
Although resulting in first pass success, the engineer always strived
to improve his cycle time through methodology adjustments.
"What are you doing?", the CAD manager of the engineer's group asked.
"I am building a new chip using Cadence tools," the engineer replied,
not without a little pride. "But I want to also perform my own place
and route and will be using the placement based synthesis package Cadence
offers; I have limited time for place and route," the engineer admitted.
The CAD manager said, "You know, Synopsys told me they are the only
synthesis vendor; they said they are the industry choice for top down
design. Since I am an expert in using Synopsys tools, I shall buy
you a copy of the Synopsys tools and teach you how to use it."
"If it will help me decrease my cycle time, please do so," responded
the engineer. The CAD manager left, returning the next morning with
not one, but three Synopsys application engineers. "The AE's
from Synopsys will train you on my new methodology," said the CAD
manager.
"Why have you brought so many AE's?" asked the engineer.
The CAD manager smiled. "You have a large IC to design. You will
need different tools to design your chip. Synopsys sells a full
line of world class products. I like to say 'the right tool for the job.'
Let me introduce each AE and then have that person describe the tools
they support." The AE's went on the introduce the engineer to
the Synopsys tools.
"I haven't written a single line Verilog code for this chip,"
the engineer said.
"We will take care of that," the CAD manager responded, and continued,
pointing to one of the Synopsys representatives that had said nothing
during the initial presentations. "This is Vic. H. DeLong, he will
teach you how to write Verilog code for Synopsys. In fact he is an
expert in writing behavioral code."
"My IC is a simple, mainly asynchronous design with internal RAM and ROM."
"No matter", said the CAD manger, frowning at the interruption.
"Synopsys has a behavioral synthesis tool that can can take full
advantage of the code you will write."
The engineer bit his lip. "Thank you for introducing me to these
world class tools. I hope I will need them. But now I would like
to start coding my design. Can you teach me how write Verilog code
that Synopsys can synthesize?"
"Yes, of course." The CAD manager sat down and attempted to log onto a
work station. After a moment he said, "This work station is not
powerful enough to run the Synopsys tools. I shall need to scrap it
and buy you another, more powerful machine."
"Will it take long?" the engineer asked. But the CAD manger had not
heard him, for he was discussing the workstation requirements with the
team from Synopsys. After a moment, the CAD manager return smiling.
"Better yet, I shall return tomorrow with a new workstation running
a new, much better operating system!"
When the CAD manager and the Synopsys team had gone, the engineer
picked up the behavioral Synopsys manual, read a few sections and started
to write some RTL Verilog code. After his first small block was finished,
the engineer attempted to fire up v3.3a of the Synopsys synthesis package
(that the AE's had loaded) only to have it crash or reject his code every time
he called the executable. He was quite frustrated and decided to walk down to
the soda machine for a drink. He returned and said to himself, "Perhaps there
is a lot more to writing code for Synopsys than this manual indicates,
the Cadence synthesis tools were not this hard to learn..." He decided
he had better wait for the CAD manager to teach him how code his design.
The next morning, the CAD manager returned with a shiny new
workstation and a half dozen or so compact disks containing the new
operating system and the Synopsys software for this OS. With great
enthusiasm, the CAD manager, apparently an expert system administrator
as well, skilled and wise in the ways of operating system administration
*and* logic synthesis, explained what needed to be loaded,
how long it would take, and why this operating system was so much better
than the old one for logic synthesis tools. The engineer listened patiently.
Inserting the first of many CD's, the CAD manager started to load
the software.
To bide his time, the engineer found an empty cubicle and logged into
the idle workstation. He decided to attempt to synthesize one of the
RTL modules he had coded earlier for his chip using the Cadence tools.
This time, since he had not really simulated this module, the Cadence
tools returned pages of errors and halted. The frustrated engineer mumbled a
few choice remarks under his breath, only to be heard by the CAD manger
who was now staring over his shoulder. The CAD manager smiled at him and
said, "Now you understand the importance of using the world class tools!"
Loading the operating system and Synopsys software took the rest of
the day. As the hour was late, the CAD manager said, "The workstation
is now ready, I shall return in the morning with the Synopsys AE's and
teach you a new, world class methodology."
"I hope so," the engineer said. The CAD manager had already departed
and missed the sarcasm in the engineer's voice.
The CAD manager arrived early the next morning. The engineer got up
from his temporary location and followed him to the new workstation with
the new operating system. "Please teach me how to use this new software.
I would like to start building my IC," said the engineer. But instead of
logging into the workstation, the CAD manager took a glossy flyer out of
his back pocket. "Read this. It describes how Synopsys links to physical
layout tools. You will use it to place and route your chip. We will have
to buy tools from Arcsys, the route engine that Synopsys recommends. High
level design technology moves quickly."
The engineer took a deep breath. "I have an IC to build," he said.
"Using the Cadence tools I would have been done with my simulations by
now. Instead, nothing has started. You seem interested only in
Synopsys. I am interested in building my IC. I would like to start
now."
The CAD manager said, "I am sorry preparing this methodology change
has taken so long. If I purchase this new router you will finish your
design long before you would have using the Cadence tools. I promise."
The engineer was torn, but, after some thought and some misgivings, he
decided he would once more trust the CAD manager - although not
completely. "Buy it," said the engineer, "and place and route this
sample net-list. If it does not work, you will return it. Agreed?"
"Agreed. I shall order the router tonite," replied the CAD manager.
A week later, the CAD manager was back with more AE's from Synopsys
and the router company. With great ceremony, the CAD manager logged
into the workstation. After a few hours of trying to get the current
standard cell library into the new router, the CAD manager declared,
"I will need to re-design the cell library to take full advantage of the
our new router."
"How long will this take?", the engineer asked.
"At least two months,", the CAD manger replied.
At this point the engineer decided he had better just agree with the
CAD manager, get him out of his way, and resume designing his IC with
the Cadence tools.
Two months later, his IC completed, taped out, and in processing. The
engineer was standing by the soda machine sipping a cold drink.
"When will your IC be out of fab?"
The engineer turned to find the CAD manager standing behind him. This
was the first time the CAD manager had ventured out of his office
since he started to re-design the standard cell library for the new
Synopsys based methodology.
"But you did not use the Synopsys tools or the new router," continues
the CAD manager.
"No," agreed the engineer. "I used the Cadence simulation, synthesis,
and place and route tools."
After an awkward pause, the CAD manager changed the subject by asking,
"What are you working on now?"
"I am designing a low power RISC microprocessor," the engineer replied.
"Synopsys has incorporated power analysis tools into their product line.
They tell me they can even pick cells that have low static power during
optimization," said the CAD manager. "Using the Synopsys tools you get
the lowest power, highest performance design in the shortest amount of time."
Sadly, feeling justified, the engineer shook his head and walked back
to his office. He immediately fired up Framemaker and entered up his
resume'; two months later the engineer was gone and the CAD manager had
replaced all the Cadence tools with Synopsys, Arcsys, and Mentor Graphics.
The CAD manager was also convinced by Synopsys to switch languages to VHDL.
The IC design engineers left struggled.
...not quite a year later, the CAD manager, his staff, and a large portion of
the design group he supported were dismissed in a layoff...
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